Presentation
A Novel Test Point Insertion Methodology for Enhanced Test Efficiency and Improved Design Quality
DescriptionDevice test cost and DPPM are of paramount importance to gain market share by offering quality devices at optimal price point. ATPG is the proven efficient structural technique for testing and diagnosing silicon failures. In large gate count devices (5M+ design flip-flops), meeting scan coverage at entitlement has been challenging, resulting in higher scan pattern count and increased test time. Random resistant fault analysis (RRFA) based test point insertion (TPI) can improve scan coverage with lower scan pattern count - a known methodology to improve device quality. However, because of sheer design size, even 2% of design flops as test-points (TPs) leads to 100k+ more flip-flops added in design, which is huge DFT area overhead. This paper focuses on novel physical and timing aware TPI methodology, strategically re-purposing pre-existing functional/DFT flops in design as TPs. Further we propose observe-only TPs to gain scan coverage in DFT infrastructure blocks. This study evaluates the methodology across range of sub-chips, utilizing benefits of TPI and demonstrating substantial improvements in test quality and test time while overcoming the shortcomings and concerns of area overhead, routing congestion and power with TPs.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall