Presentation
AI/ML Driven Optimization for Efficient ATPG in Large Scale Designs
DescriptionLSF Resource Optimization in Large-Scale Designs: Generating ATPG for complex designs (e.g., 5M+ flip-flops) is time-consuming, creating bottlenecks in meeting tight project timelines. AI/ML solutions can dynamically allocate resources during Distributed Automatic Test Pattern Generation (D-ATPG) to optimize compute farm usage, significantly reducing turnaround time (TAT).
Design Rule(DRC) Check and Simulation dashboard Automation: In large gate count designs, it becomes challenging to disposition scan ATPG Design Rule Checks (DRCs) and simulation results across corners & multiple handoffs (15+ releases). Once the DRCs are analyzed, manual dispositioning of these DRCs repeatedly across multiple handoffs is time consuming and wastage of resources. Identifying new violations is difficult with manual checks across thousands of violations in multiple ATPG testmode DRC log files.
DFT Simulations Quality check involves analysis of huge amount of data such as pass/fail result, failure pattern type, runtime, mem usage and so on from thousands of simulation runs. This takes significant man hour effort and error prone.
Low Power ATPG Efficiency: ATPG processes often lead to excessive switching activity, increasing IR drop and potentially causing pattern failures. AI/ML can predict and adapt test patterns for low-power scenarios, reducing power consumption while maintaining test quality and coverage.
Scan Coverage and Pattern Count Reduction: Test points implementation has been used in the past for improving controllability and observability in the design, thus improving scan coverage and optimize pattern count. Traditional manual methods of identifying test points are resource-intensive and might not be the most optimal. AI/ML algorithms can intelligently identify the optimal test points, improving scan coverage while minimizing pattern count, thereby cutting down test time and cost.
Accelerated Decision-Making for Optimal Test Strategies: AI/ML models can analyze massive amounts of data from previous ATPG runs to derive insights, enabling faster and more accurate decisions for optimal test pattern generation and resource utilization, enhancing overall ATPG efficiency and reliability.
Design Rule(DRC) Check and Simulation dashboard Automation: In large gate count designs, it becomes challenging to disposition scan ATPG Design Rule Checks (DRCs) and simulation results across corners & multiple handoffs (15+ releases). Once the DRCs are analyzed, manual dispositioning of these DRCs repeatedly across multiple handoffs is time consuming and wastage of resources. Identifying new violations is difficult with manual checks across thousands of violations in multiple ATPG testmode DRC log files.
DFT Simulations Quality check involves analysis of huge amount of data such as pass/fail result, failure pattern type, runtime, mem usage and so on from thousands of simulation runs. This takes significant man hour effort and error prone.
Low Power ATPG Efficiency: ATPG processes often lead to excessive switching activity, increasing IR drop and potentially causing pattern failures. AI/ML can predict and adapt test patterns for low-power scenarios, reducing power consumption while maintaining test quality and coverage.
Scan Coverage and Pattern Count Reduction: Test points implementation has been used in the past for improving controllability and observability in the design, thus improving scan coverage and optimize pattern count. Traditional manual methods of identifying test points are resource-intensive and might not be the most optimal. AI/ML algorithms can intelligently identify the optimal test points, improving scan coverage while minimizing pattern count, thereby cutting down test time and cost.
Accelerated Decision-Making for Optimal Test Strategies: AI/ML models can analyze massive amounts of data from previous ATPG runs to derive insights, enabling faster and more accurate decisions for optimal test pattern generation and resource utilization, enhancing overall ATPG efficiency and reliability.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall