Presentation
Hierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC Structures
DescriptionAs the technology nodes shrink, and chips scale up in size and PDN nodes, simulating IR-drop has faced challenges to ensure high coverage while optimizing infrastructure usage. IR-drop analysis at full-chip level for large SoCs takes days of runtime even with high number of cores. Meanwhile, developments of 2.5DIC and 3DIC technologies posed various complexities. In this regard, we require methodologies which enable concurrent IR-drop analysis of die, interposer and package, while optimized in runtime and computational resources.
In this work, we present a hierarchical IR-drop analysis for a 2.5DIC structure comprised of a compute die on an organic interposer. In this approach, we deployed Reduced Order Model (ROM) methodology which creates an abstract view of hierarchical blocks and consumes these models at top-level to run full-chip IR analysis. We simulated the Die+Interposer+Package structure by using only ROM for each block of the die (100% ROM) and instantiating them at the die top-level. Using this solution, design node count was reduced significantly (98.9%) compared to full-chip flat analysis, improving analysis runtime by 86%, and reducing total physical machine memory by 89%. The proposed methodology provides faster turnaround time and lower infrastructure cost addressing the demands of modern large SoC designs.
In this work, we present a hierarchical IR-drop analysis for a 2.5DIC structure comprised of a compute die on an organic interposer. In this approach, we deployed Reduced Order Model (ROM) methodology which creates an abstract view of hierarchical blocks and consumes these models at top-level to run full-chip IR analysis. We simulated the Die+Interposer+Package structure by using only ROM for each block of the die (100% ROM) and instantiating them at the die top-level. Using this solution, design node count was reduced significantly (98.9%) compared to full-chip flat analysis, improving analysis runtime by 86%, and reducing total physical machine memory by 89%. The proposed methodology provides faster turnaround time and lower infrastructure cost addressing the demands of modern large SoC designs.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall