Presentation
Enhanced LVS Techniques for Fast Convergence and Optimized Design Cycles
DescriptionIn the realm of integrated circuit (IC) design, the efficiency and accuracy of Layout Versus Schematic (LVS) extraction are critical for ensuring design integrity and functionality. Handling LVS for cutting-edge automotive designs presents significant challenges due to the resource-intensive nature of "dirty" designs, which require high runtime and memory. The presence of shorts and high comparison times in these designs drives up physical verification (PV) cycles, leading to substantial delays in the turnaround time at the sign-off stage.
A recent case study highlights the stark contrast between LVS extraction and traditional comparison methods. The LVS extraction process was completed in a remarkable 5 hours, demonstrating its efficiency and reliability. In contrast, the traditional comparison method failed to complete even after running for 2 days, ultimately aborting due to excessive memory consumption exceeding 2TB. This significant disparity underscores the urgent need for more efficient LVS extraction techniques in IC design.
Several features have been implemented to improve performance and accuracy. These include generating an automatic list of hierarchical cells (hcells) for hierarchical LVS comparison and removing hcells causing false discrepancies. This approach reduces the list of hcells for the comparison stage, leading to shorter runtimes. Additionally, it is crucial to identify and isolate text shorts in the early stages of design. Techniques such as Detect Shorts Through High-Resistance Layers (LVS Softchk) and performing Electrical Rule Checks (ERC) ensure compliance with specified rules, reducing runtime, memory usage, and debugging complexity compared to normal LVS batch runs.
A recent case study highlights the stark contrast between LVS extraction and traditional comparison methods. The LVS extraction process was completed in a remarkable 5 hours, demonstrating its efficiency and reliability. In contrast, the traditional comparison method failed to complete even after running for 2 days, ultimately aborting due to excessive memory consumption exceeding 2TB. This significant disparity underscores the urgent need for more efficient LVS extraction techniques in IC design.
Several features have been implemented to improve performance and accuracy. These include generating an automatic list of hierarchical cells (hcells) for hierarchical LVS comparison and removing hcells causing false discrepancies. This approach reduces the list of hcells for the comparison stage, leading to shorter runtimes. Additionally, it is crucial to identify and isolate text shorts in the early stages of design. Techniques such as Detect Shorts Through High-Resistance Layers (LVS Softchk) and performing Electrical Rule Checks (ERC) ensure compliance with specified rules, reducing runtime, memory usage, and debugging complexity compared to normal LVS batch runs.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall