Presentation
Optimizing Power Integrity with Smart PDN Framework
DescriptionThe rapid pace of product development necessitates minimizing time to market, often constraining the time available for Physical Design and Signoff (PDN, STA, and Physical Verification). This challenge is exacerbated as the semiconductor industry transitions to advanced technology nodes such as 5nm and 3nm, where robust PDN is essential for ensuring chip reliability in diverse applications, including laptops, cloud servers, AI, mobile devices, automotive systems, medical equipment, and wearables. The increasing design complexity and stringent performance requirements necessitate extensive PDN checks across multiple Voltage-Controlled Domains (VCDs), functional and test modes, and process-voltage-temperature (PVT) corners, significantly extending simulation and debugging times. Addressing Electromigration (EM) and IR drop issues within compressed timelines, while managing the high volume of intricate designs, presents substantial challenges, particularly given the specialized nature of PDN and the limited availability of skilled engineers in this domain.
To mitigate these challenges, the "Smart PDN Framework" has been developed and implemented. This advanced solution enhances efficiency by facilitating comprehensive PDN checks, ensuring the integrity of simulation runs, and continuously monitoring the PDN status of each design block across all checks. By streamlining the debugging process and expediting fixes, the Smart PDN Framework significantly improves turnaround time and signoff quality, thereby meeting the critical demands of contemporary product development cycles.
To mitigate these challenges, the "Smart PDN Framework" has been developed and implemented. This advanced solution enhances efficiency by facilitating comprehensive PDN checks, ensuring the integrity of simulation runs, and continuously monitoring the PDN status of each design block across all checks. By streamlining the debugging process and expediting fixes, the Smart PDN Framework significantly improves turnaround time and signoff quality, thereby meeting the critical demands of contemporary product development cycles.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall