Presentation
Reducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE Technology
DescriptionA High Frequency Clock Generator is an integral part of such electronic circuits and plays a crucial role in defining the performance of the overall system. Today, designers are facing below challenges while doing verification of high frequency PLL designs,
1. For critical RF analog applications covering targeting frequencies upto 20GHz the simulation runtime time with spice solver can go upto a month. This motivates designers to explore other techniques which are prone to modelling and interpolation errors for which extra design margins are taken into account which eventually lead to over-designs.
2. Top level Cross Corner Simulations to cover various PVTs further increases the verification time.
3. Jitter measurement becomes extremely complex typically in sub-ps range. This forces a tight constraint on the max step size such that simulator must ensure during threshold crossing.
4. Incorporate supply (RLC) network to mimic exact SOC behavior especially, Inductors which can be tricky.
This paper extensively studies the use of new enhanced Fast-SPICE simulator (Spectre-FX) on Charge-Pump Based PLL Design which shows close to spice accuracy and can also do clock jitter and phase noise verification in presence of supply inductive network without compromising on accuracy with an impressive 15.3X performance gain.
1. For critical RF analog applications covering targeting frequencies upto 20GHz the simulation runtime time with spice solver can go upto a month. This motivates designers to explore other techniques which are prone to modelling and interpolation errors for which extra design margins are taken into account which eventually lead to over-designs.
2. Top level Cross Corner Simulations to cover various PVTs further increases the verification time.
3. Jitter measurement becomes extremely complex typically in sub-ps range. This forces a tight constraint on the max step size such that simulator must ensure during threshold crossing.
4. Incorporate supply (RLC) network to mimic exact SOC behavior especially, Inductors which can be tricky.
This paper extensively studies the use of new enhanced Fast-SPICE simulator (Spectre-FX) on Charge-Pump Based PLL Design which shows close to spice accuracy and can also do clock jitter and phase noise verification in presence of supply inductive network without compromising on accuracy with an impressive 15.3X performance gain.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall