Presentation
Revolutionising SOC Verification through System Verilog EEnet-Enhanced Behavioural Model for Precision in Analog IP Characterisation
DescriptionOur work presents a novel SV EEnet methodology leveraging the Cadence EEnet net type to model current and voltage on a single net, enabling accurate transistor-level modeling and efficient identification of non-idealities such as loading and coupling. By accurately representing the Analog Test Bus (ATB) path, our approach enhances Digital Mixed-Signal (DMS) co-simulations for ATB verification.
This advancement significantly reduces the reliance on Analog Mixed-Signal (AMS) co-simulations, simplifying the verification process.
The methodology can be used and implemented by all the mixed-signal SoCs to expedite the process of behavioural model generation with better accuracy to the conventional VAMS models. It leads to reduction of the execution cycle time and higher coverage in AMS co-simulations by covering scenarios which were earlier incomprehensible in DMS co-sim.
This advancement significantly reduces the reliance on Analog Mixed-Signal (AMS) co-simulations, simplifying the verification process.
The methodology can be used and implemented by all the mixed-signal SoCs to expedite the process of behavioural model generation with better accuracy to the conventional VAMS models. It leads to reduction of the execution cycle time and higher coverage in AMS co-simulations by covering scenarios which were earlier incomprehensible in DMS co-sim.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall