Presentation
Expediting custom core SOC verification and coverage driven firmware sign-off using ESWD & Verisium Debug
DescriptionWith emergence of complex SOC designs, the challenges in verification have increased manifold, which involves multiple instances of custom core CPUs at SOC. Adherence to aggressive schedules holds utmost importance for platform devices. With no margin for error, first pass Silicon for custom CPU designs enables early breakthroughs in automotive, industrial, high-performance compute (HPC) and artificial intelligence applications. As the complex world of CPU clusters forays into paradigm shifting capabilities in ASIC designs, hardware-software co-debug continues to become a ubiquitous need of the hour. In this regard, Cadence Embedded Software Debug (ESWD) aids in expediting custom core-based SOC verification closure by coverage-driven firmware signoff and ease of debug for CPU execution which ensures systematic traceability of test coverage compared to erstwhile art of manual directed tests mapping in test plan for features covered. ESWD paved the way for faster debugs and unfolding corner case scenarios when the compiler scripts and platform SOC development executes in parallel. The detailed paper will highlight the achieved results with debug capabilities and impact for custom core SOC platform developments.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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