Presentation
A constructive approach to Left-shift preliminary identification of critical silicon breaking anomalies
DescriptionWith myriad complex SOCs, challenges in verification have increased manifold. One of the challenging aspects of any SOC/IP verification is to identify the un-initialized flops in a design and analyze them across all corner case scenarios which, if not taken care, can lead to catastrophic silicon issues. Most of these when caught on silicon leads to re-spin of the device.
Hence it becomes extremely important to identify such cases in the design, either in RTL phase or gate-level simulations and analyze their impact on the design with due-diligence. There have been multiple cases where potential issues got masked due to random deposits in gate-level simulations, hence escaping to silicon.
With SOC integration levels approaching a billion transistors per chip, tremendous pressure to shrink the verification cycle, and power minimization, it becomes important to identify and resolve such potential bugs due to un-initialized/non-resettable flops in RTL verification stage (early enough in design cycle).
Following paper proposes a complete & practical methodology along with case studies over various SOC silicon findings for early identification and left shift of potential silicon bugs that could easily escape due to un-initialized flops in any SOC.
Here we leverage different tool support from Cadence and come up with a methodology to which helps to identify potential bugs.
With case-studies done on various Silicon bugs, this novel methodology has proved to effectively catch those un-initialized flops at RTL design stage itself.
Hence it becomes extremely important to identify such cases in the design, either in RTL phase or gate-level simulations and analyze their impact on the design with due-diligence. There have been multiple cases where potential issues got masked due to random deposits in gate-level simulations, hence escaping to silicon.
With SOC integration levels approaching a billion transistors per chip, tremendous pressure to shrink the verification cycle, and power minimization, it becomes important to identify and resolve such potential bugs due to un-initialized/non-resettable flops in RTL verification stage (early enough in design cycle).
Following paper proposes a complete & practical methodology along with case studies over various SOC silicon findings for early identification and left shift of potential silicon bugs that could easily escape due to un-initialized flops in any SOC.
Here we leverage different tool support from Cadence and come up with a methodology to which helps to identify potential bugs.
With case-studies done on various Silicon bugs, this novel methodology has proved to effectively catch those un-initialized flops at RTL design stage itself.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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