Presentation
"Optimizing Timing Convergence in High-Speed PCIe Systems: An EDA Methodological Approach"
DescriptionThis work discusses optimized placement methodology to achieve faster timing convergence and enhanced synchronization in PCIe sub system. The latency of data transmission plays a crucial role, and data transfer rates have significantly improved with standards like PCI Express. The physical implementation of PCI Express presents significant challenges, particularly due to the aspect ratio, limited routing resources, and the number of clocks in the design. We present an innovative
approach that simplifies the implementation of multilane PCIe systems. The challenges at each stage are identified, and corresponding solutions are proposed here. Initially, we employ a source synchronous approach to achieve synchronization between the data and clock nets, followed by structural based placement methodology that enhances the implementation process. The proposed methodology systematically eliminates crosstalk issues, reduces skew by 33%, decreases the depth of data and clock paths by 30%, achieves better timing convergence and reduced the turnaround time by 41%, thereby optimizing overall design performance.
approach that simplifies the implementation of multilane PCIe systems. The challenges at each stage are identified, and corresponding solutions are proposed here. Initially, we employ a source synchronous approach to achieve synchronization between the data and clock nets, followed by structural based placement methodology that enhances the implementation process. The proposed methodology systematically eliminates crosstalk issues, reduces skew by 33%, decreases the depth of data and clock paths by 30%, achieves better timing convergence and reduced the turnaround time by 41%, thereby optimizing overall design performance.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall