Presentation
A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
DescriptionIn high-speed design we need to do manual eco to meet last miles timing paths. Pipeline Retiming is an optimization technique involves splitting and repositioning of combinational logic across the sequential without changing its logical functionality.
Current EDA Logical Equivalence Check (LEC) Tools has limitation to verify equivalence on sequential retiming because required information does not get saved in json file.
To overcome the above limitation of EDA vendor tool we are proposing a method to verify logical equivalence check after pipeline retiming, which helped to improve the frequency limiting paths by 2% of cycle time
Current EDA Logical Equivalence Check (LEC) Tools has limitation to verify equivalence on sequential retiming because required information does not get saved in json file.
To overcome the above limitation of EDA vendor tool we are proposing a method to verify logical equivalence check after pipeline retiming, which helped to improve the frequency limiting paths by 2% of cycle time
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall