Presentation
Design Floorplan-Driven Localization of SMS Processors for Optimized Memory Performance
DescriptionThis work addresses the challenges of timing convergence and routing congestion in modern memory systems by introducing a localized approach to STAR (Self-Test and Repair) Memory System (SMS) processor placement. SMS processors are essential components that enable efficient testing, error detection, and repair in memory architectures. However, traditional centralized STAR architectures often face challenges in timing and design convergence due to high load and extensive interconnects, leading to routing complexity and performance bottlenecks.
To overcome these issues, we propose splitting and localizing STAR processors based on the design floorplan and memory arrangement, guided by feedback from structural designers. By strategically distributing processors closer to their associated memory blocks, our approach reduces interconnect lengths, alleviates routing congestion, and balances load across processors.
Quantitative analysis reveals a reduction in Worst Negative Slack (WNS) by ~85%, a 63% decrease in routing congestion density, and a 74% reduction in Design Rule Check (DRC) violations. Additionally, design turnaround time improved significantly due to fewer iterations and faster convergence.
This method provides a scalable solution for optimizing performance in complex memory architectures, such as SRAM and TCAM, and lays the foundation for future advancements in STAR processor design for emerging technologies.
To overcome these issues, we propose splitting and localizing STAR processors based on the design floorplan and memory arrangement, guided by feedback from structural designers. By strategically distributing processors closer to their associated memory blocks, our approach reduces interconnect lengths, alleviates routing congestion, and balances load across processors.
Quantitative analysis reveals a reduction in Worst Negative Slack (WNS) by ~85%, a 63% decrease in routing congestion density, and a 74% reduction in Design Rule Check (DRC) violations. Additionally, design turnaround time improved significantly due to fewer iterations and faster convergence.
This method provides a scalable solution for optimizing performance in complex memory architectures, such as SRAM and TCAM, and lays the foundation for future advancements in STAR processor design for emerging technologies.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall