Presentation
A Safety Centric approach to Functional Verification of Dual Core Lock-Step Designs
DescriptionASIL requirements for automotive chips have resulted in implementation of functional safety features in several IPs. Dual Core Lock Step (DCLS) is one of the popular methods to achieve functional safety in medium to large IPs which require fine grain control. With many IPs incorporating DCLS, the verification effort has increased exponentially over the years. This paper proposes a methodology to speed up the verification process by automating testbench generation and identifying potential issues early in the design cycle. The generated testbench components viz checker, error injector, scoreboard and driver, are SV/UVM compatible allowing easy integration into existing legacy testbenches. The python based automation script also provides valuable insights into the lockstep design by generating several reports for review with the designer and functional safety experts. A mathematical model is developed for evaluating the effectiveness of DCLS in detecting drift between the primary and redundant cores. The methodology is evaluated for numerous styles of DCLS implementations, and enhancement knobs are introduced to reduce automation runtimes. The proposed methodology reduces the verification effort and time by several folds.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall