Presentation
Automated AI-ML based flow for Validated Constraint Generation for CDC/RDC
DescriptionThe paper proposes an automated flow, which combines AI/ML-based constraint
generation and SV assertion-based constraint validation, to provide users with accurate
CDC/RDC constraints without manual intervention. These constraints are formally
validated. The approach targets assumptions in the design that are challenging to be
validated structurally, prompting users to provide these constraints.
Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) problems are
common issues in modern digital design, especially in designs employing multiple clock
domains. Modern SoC design often utilizes numerous underlying IPs and subsystems that
operate asynchronously with clocks, resets, and interrupts. This gives rise to multiple CDC
and RDC signals crossing clock and reset domain boundaries.
Advanced CDC/RDC tools provide smart structural analysis of RTL designs, which
can be further validated formally for protocol verification. This analysis significantly depends
on tool-specific design constraints like clock-reset definition, gray encoding, stable signals,
and constant signals, etc.
In the context of ASIC design flow, static validation tools identify specific structures
that may cause metastability or data coherence problems at runtime. With advances in
artificial intelligence and machine learning, leading industry tools offer AI/ML-based utilities
to generate or locate missing CDC/RDC constraints. However, the complexity of validating
these generated constraints remains a challenge.
The proposed solution suggests integrating the available technologies of AI/ML-
based constraint generation and SV assertion-based constraint validation into an
automated "push-button" flow. This reduces the need for human intervention in generating
and validating CDC/RDC constraints. The paper focuses on targeting assumptions that are
difficult to validate structurally and expects users to provide these constraints.
When we discuss constraints, their sources can vary. Examples include:
1. Boundary assumptions that are beyond the designer's control and cannot be
generated by the tool as SV assumptions. For example, input clock port frequency
and input port domain clock association.
2. Boundary assumptions provided as design guidelines that can be converted into SV
assumptions by available tools, such as constant values and static with respect to
the clock.
3. Behavior on internal nets and registers based on design behavior that can be analyzed
in structural analysis, such as clock domain association.
4. Assumptions on internal nets and registers based on design functionality, which will
be forced during runtime depending on the design modes and are challenging to
validate structurally, such as gray-encoded address buses, internal functional
constants, and reset orders.
In this paper, the primary focus is on Category 4 above. The constraints generated will be
supported by converting SV assertions mentioned in Category 2 for complete closure.
We plan to analyze available solutions for AI-ML based constraint generation and the
types of constraints generated by them. With machine-generated constraints, we will first
explore the design-specific constraints that can be easily validated using SV assertions.
Next, we will run static analysis with the automatically generated constraints and explore
available tools to generate SV assertions for specific validation of these constraints. The
process will be automated using TCL scripts for push-button functionality:
1. Run the optimized first cut CDC/RDC structural analysis.
2. Automatically execute the AI-ML based tool to generate constraints.
3. Filter out constraints satisfying Category 4 above.
4. Append these constraints to the available constraints for the first cut run and rerun
the CDC/RDC analysis.
5. Automatically generate SV assertions for added constraints and run formal analysis.
6. Filter out failing constraints and rerun the CDC/RDC analysis with passing
constraints only.
Vacuous Formal properties can be explored for additional support of category
2 assumptions above.
7. Automate this entire flow with TCL scripts for a push-button methodology.
8. Solution will also explore the support of hierarchal design methodology to assist large
SoC designs.
The results of this paper include:
• A set of constraints that are true by design and do not require manual application in
CDC/RDC analysis, helping automate a significant part of manual effort for
CDC/RDC engineers.
• Integration of two available technologies to achieve faster closure time for projects
already on critical paths.
• Opening up the possibility of automating more constraints in the future based on
advancements in AI-ML tools, making this a step in the right direction.
• Formal validation of constraints that eliminate the risk of bad CDC/RDC constraints
and redirect user effort towards addressing actual problems.
Future work will cover all available possibilities for tool-based constraint generation and
highlight best-case scenarios readily amenable to formal validation.
generation and SV assertion-based constraint validation, to provide users with accurate
CDC/RDC constraints without manual intervention. These constraints are formally
validated. The approach targets assumptions in the design that are challenging to be
validated structurally, prompting users to provide these constraints.
Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) problems are
common issues in modern digital design, especially in designs employing multiple clock
domains. Modern SoC design often utilizes numerous underlying IPs and subsystems that
operate asynchronously with clocks, resets, and interrupts. This gives rise to multiple CDC
and RDC signals crossing clock and reset domain boundaries.
Advanced CDC/RDC tools provide smart structural analysis of RTL designs, which
can be further validated formally for protocol verification. This analysis significantly depends
on tool-specific design constraints like clock-reset definition, gray encoding, stable signals,
and constant signals, etc.
In the context of ASIC design flow, static validation tools identify specific structures
that may cause metastability or data coherence problems at runtime. With advances in
artificial intelligence and machine learning, leading industry tools offer AI/ML-based utilities
to generate or locate missing CDC/RDC constraints. However, the complexity of validating
these generated constraints remains a challenge.
The proposed solution suggests integrating the available technologies of AI/ML-
based constraint generation and SV assertion-based constraint validation into an
automated "push-button" flow. This reduces the need for human intervention in generating
and validating CDC/RDC constraints. The paper focuses on targeting assumptions that are
difficult to validate structurally and expects users to provide these constraints.
When we discuss constraints, their sources can vary. Examples include:
1. Boundary assumptions that are beyond the designer's control and cannot be
generated by the tool as SV assumptions. For example, input clock port frequency
and input port domain clock association.
2. Boundary assumptions provided as design guidelines that can be converted into SV
assumptions by available tools, such as constant values and static with respect to
the clock.
3. Behavior on internal nets and registers based on design behavior that can be analyzed
in structural analysis, such as clock domain association.
4. Assumptions on internal nets and registers based on design functionality, which will
be forced during runtime depending on the design modes and are challenging to
validate structurally, such as gray-encoded address buses, internal functional
constants, and reset orders.
In this paper, the primary focus is on Category 4 above. The constraints generated will be
supported by converting SV assertions mentioned in Category 2 for complete closure.
We plan to analyze available solutions for AI-ML based constraint generation and the
types of constraints generated by them. With machine-generated constraints, we will first
explore the design-specific constraints that can be easily validated using SV assertions.
Next, we will run static analysis with the automatically generated constraints and explore
available tools to generate SV assertions for specific validation of these constraints. The
process will be automated using TCL scripts for push-button functionality:
1. Run the optimized first cut CDC/RDC structural analysis.
2. Automatically execute the AI-ML based tool to generate constraints.
3. Filter out constraints satisfying Category 4 above.
4. Append these constraints to the available constraints for the first cut run and rerun
the CDC/RDC analysis.
5. Automatically generate SV assertions for added constraints and run formal analysis.
6. Filter out failing constraints and rerun the CDC/RDC analysis with passing
constraints only.
Vacuous Formal properties can be explored for additional support of category
2 assumptions above.
7. Automate this entire flow with TCL scripts for a push-button methodology.
8. Solution will also explore the support of hierarchal design methodology to assist large
SoC designs.
The results of this paper include:
• A set of constraints that are true by design and do not require manual application in
CDC/RDC analysis, helping automate a significant part of manual effort for
CDC/RDC engineers.
• Integration of two available technologies to achieve faster closure time for projects
already on critical paths.
• Opening up the possibility of automating more constraints in the future based on
advancements in AI-ML tools, making this a step in the right direction.
• Formal validation of constraints that eliminate the risk of bad CDC/RDC constraints
and redirect user effort towards addressing actual problems.
Future work will cover all available possibilities for tool-based constraint generation and
highlight best-case scenarios readily amenable to formal validation.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall