Presentation
MCP Induced Glitches
DescriptionModern Multi-Processor Systems on Chip (MPSoCs) comprise multiple clock domains involving synchronous and asynchronous data paths. Glitches in asynchronous clock domain crossings are very well known and there are state-of-the-art industry signoff tools to cover them.
However, the synchronous logic is also susceptible to glitches due to Multi-Cycle Paths, MCPs in design.
MCP verification and detection of invalid or incorrectly implemented MCPs is not feasible at Gate Level Simulations. Industry available tools target MCP verification at the RTL level and netlist restructuring limits their applicability. Running these tools on netlist causes an exponential explosion of reported violations making it non-feasible to complete within the tight SoC design timelines.
Incorrectly implemented or invalid MCPs can cause unintended design behavior or the device might end up getting stuck or hung or even dead.
The methodology presented targets to resolve the issues due to glitches in MCPs. The flow makes use of STA shell to check the correctness of MCPs. It can be deployed to identify invalid and incorrectly implemented MCPs at gate level netlist level. Additionally, the flow can be used to functionally verify the accuracy of MCPs. The flow is scalable and has been tested across various-sized SoCs.
However, the synchronous logic is also susceptible to glitches due to Multi-Cycle Paths, MCPs in design.
MCP verification and detection of invalid or incorrectly implemented MCPs is not feasible at Gate Level Simulations. Industry available tools target MCP verification at the RTL level and netlist restructuring limits their applicability. Running these tools on netlist causes an exponential explosion of reported violations making it non-feasible to complete within the tight SoC design timelines.
Incorrectly implemented or invalid MCPs can cause unintended design behavior or the device might end up getting stuck or hung or even dead.
The methodology presented targets to resolve the issues due to glitches in MCPs. The flow makes use of STA shell to check the correctness of MCPs. It can be deployed to identify invalid and incorrectly implemented MCPs at gate level netlist level. Additionally, the flow can be used to functionally verify the accuracy of MCPs. The flow is scalable and has been tested across various-sized SoCs.
Event Type
Engineering Presentation
TimeTuesday, June 2411:45am - 12:00pm PDT
Location2012, Level 2