Presentation
An engineering approach to high performance scannable flip flops embedding functional logics
DescriptionOn logic embedding in semi-dynamic flip-flops, this paper identifies two main issues: slow evaluation time in an dynamic stage and unwanted glitch at an output node. To address these issues, this paper proposes novel scannable semi-dynamic flip-flops featuring a two-stack NMOS in the dynamic stage, whereas conventional semi-dynamic flip-flops typically use three or more stacks to incorporate a scan MUX. Moreover, the paper introduces a new scannable logic-embedded flip-flop that adopts a modified clock-delayed domino, which is specifically designed to suppress the unwanted glitch while also enhancing speed. The proposed scannable two-stack semi-dynamic flip-flop improves data-to-output latency by 56%, as demonstrated by 14nm FinFET silicon measurement results, compared to a conventional master-slave flip-flop with the scan MUX. Even when incorporating complex logic, the proposed scannable logic-embedded flip-flop achieves nearly the same D-to-Q latency as a conventional static pulse-based flip-flop, which only includes the scan MUX. The measurement results also show that the glitch width at the output node of the proposed scannable logic-embedded flip-flop is reduced by 3 to 5 times, attributable to the two-stack NMOS and modified clock-delayed domino structures.
Event Type
Engineering Presentation
TimeMonday, June 234:15pm - 4:30pm PDT
Location2010, Level 2