Presentation
A Novel Solution for Parasitic resistance analysis: Calibre PERC-Driven Optimization for PEX Quality Assurance
DescriptionLVS (Layout vs. Schematic) and PEX (Parasitic Extraction) verification has to ensure accurate circuit layout alignment and extraction of parasitic elements. Advanced LVS/PEX techniques, including parasitic elements, improve Model-to-Hardware Correlation (MHC) for accurate design closure and manufacturing control. However, At GAA(Gate-All-Around) technology node the increase in the number of derived FEOL (Front End of Line) and MOL (Middle End of Line) layers poses challenges in Parasitic Resistance and ensuring no PEX Quality, thus affecting Process Design Kit (PDK) release schedules. In response to this, We propose an innovative method to verify the parasitic resistance-related issues in layouts utilizing the pin-to-pin functionality of PERC (Programmable Electrical Rule check). This approach safeguards Parasitic Resistance benefits, reinforces manufacturing control, and adeptly addresses challenges associated with parasitic resistance-related issues in advanced semiconductor designs.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall