Presentation
Comprehensive Interconnect Verification – Leveraging Formal Methodology & Automation for verifying Address Decoding and Arbiter Verification, Performance Analysis
DescriptionInterconnects are among the most critical IPs in any system-on-chip (SoC) design, directly impacting overall performance and functionality. The increasing complexity of interconnect architectures, coupled with stringent performance requirements, poses significant challenges to traditional verification methodologies. In this work, we present a comprehensive verification flow tailored for interconnects, designed to improve both design and verification quality.
Our flow integrates formal verification methodologies to ensure data integrity and leverages Universal Verification Methodology (UVM) components to generate detailed performance and arbitration reports. These reports provide actionable insights into interconnect behavior and performance metrics. The proposed solution is scalable, automated, and adaptable to various interconnect designs, making it a one-stop solution for holistic interconnect verification. Through this approach, we enable designers and verification engineers to meet the demands of modern SoC architectures efficiently and reliably.
Our flow integrates formal verification methodologies to ensure data integrity and leverages Universal Verification Methodology (UVM) components to generate detailed performance and arbitration reports. These reports provide actionable insights into interconnect behavior and performance metrics. The proposed solution is scalable, automated, and adaptable to various interconnect designs, making it a one-stop solution for holistic interconnect verification. Through this approach, we enable designers and verification engineers to meet the demands of modern SoC architectures efficiently and reliably.
Event Type
Engineering Presentation
TimeTuesday, June 242:45pm - 3:00pm PDT
Location2010, Level 2
Front-End Design