Presentation
Robust Verification for Complex Liberty IP
DescriptionFoundational IP design of standard cells, memory's, IOs and more are a crucial component for SoC design. The foundational IPs in question can have numerous views, one of which is liberty, a representation of timing, power, noise compiled within a cell library. Due to the advancement of technology, Liberty data has increased in complexity including appropriate representations within cell libraries. This added complexity can take into account data such as noise, waveforms, and statistical variation.
Some of the aforementioned data can be difficult to interpret and analyze which can often be a bottleneck in the first stages of the design. As such, ease of use and accuracy for validating this data is crucial to minimize the time spent in the QA process and reduce overall cycle time.
This presentation elaborates on a solution embedded into NXPs QA flow to alleviate the most difficult properties of verification, which include:
1. QA of complex cells in the most advanced tech nodes
2. Analysis of intricate EDA data such as LVF, moments, and CCS
3. Detection of errors, specifically outliers in liberty data with AI
Some of the aforementioned data can be difficult to interpret and analyze which can often be a bottleneck in the first stages of the design. As such, ease of use and accuracy for validating this data is crucial to minimize the time spent in the QA process and reduce overall cycle time.
This presentation elaborates on a solution embedded into NXPs QA flow to alleviate the most difficult properties of verification, which include:
1. QA of complex cells in the most advanced tech nodes
2. Analysis of intricate EDA data such as LVF, moments, and CCS
3. Detection of errors, specifically outliers in liberty data with AI
Event Type
Engineering Presentation
TimeMonday, June 234:45pm - 5:00pm PDT
Location2010, Level 2
IP