Presentation
Cross-die timing methodology for Next-Gen Chiplet SOCs - A shift-left solution for cross-foundry 3DIC-STA Signoff
DescriptionAdoption of advanced packaging has accelerated multi-chip module (MCM) based heterogeneous SoC solutions. With standardization of Die to Die (D2D) interfaces such as UCIe, Industry is aggressively designing Chiplet dies involving multiple vendors, foundries, tech nodes and process corners. Due to shorter interconnect distance, these dies can communicate with each other using a source-synchronous clock-forwarding architecture PHY. Effectively making a launch & capture cross-die timing path originating at one die and ending at the other.
Due to lack of proper cross-die STA signoff methodology, we are forced to adopt pessimistic guard-banding approach, which won't scale correctly with higher data rates. A new methodology for design & signoff at package level is the need of the hour. Link budgeting based on channel ISI/cross-talk/jitter and eye-plot are still integral part of the design flow. However, the silicon correlation data did show that power-efficient source-synchronous short-reach PHY can open the possibility of STA margining methodology accounting for all the error components of link budget in future, leading to a new era of shift-left automation in custom work force.
The proposed 3DIC STA solution is foundry, tech-node and process agonistic – thereby enabling universal interoperability at Chiplet package level along with silicon proven accuracy.
Due to lack of proper cross-die STA signoff methodology, we are forced to adopt pessimistic guard-banding approach, which won't scale correctly with higher data rates. A new methodology for design & signoff at package level is the need of the hour. Link budgeting based on channel ISI/cross-talk/jitter and eye-plot are still integral part of the design flow. However, the silicon correlation data did show that power-efficient source-synchronous short-reach PHY can open the possibility of STA margining methodology accounting for all the error components of link budget in future, leading to a new era of shift-left automation in custom work force.
The proposed 3DIC STA solution is foundry, tech-node and process agonistic – thereby enabling universal interoperability at Chiplet package level along with silicon proven accuracy.
Event Type
Engineering Presentation
TimeMonday, June 231:30pm - 1:45pm PDT
Location2010, Level 2
AI
IP
Chiplet