Presentation
A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment
DescriptionVerifying a System on Chip (SoC) with embedded non-volatile memory (NVM) requires numerous tests to cover a wide range of scenarios. Traditional methods involve manually setting NVM content or using custom scripts, which are labor-intensive and inflexible.
We developed an automated flow that generates random or constrained NVM content to verify all possible values, and allows easy modification based on specific tests.
Our approach uses a spreadsheet to define NVM structure, read by an open-source language to generate a UVM Verification IP (VIP) with the expected memory structure and covergroups. This VIP automatically constructs NVM content sector by sector, eliminating manual bit-by-bit modifications. Additional files handle data constraints and randomization, used by the simulator in specific UVM phases to generate the NVM data.
This method provides control over NVM content within the UVM framework, independent of simulation tools and programming languages. It achieves comprehensive coverage and drastically reduces the time required for generating NVM content. The innovative approach enhances silicon quality and prevents bugs, making it a versatile solution for any project.
We developed an automated flow that generates random or constrained NVM content to verify all possible values, and allows easy modification based on specific tests.
Our approach uses a spreadsheet to define NVM structure, read by an open-source language to generate a UVM Verification IP (VIP) with the expected memory structure and covergroups. This VIP automatically constructs NVM content sector by sector, eliminating manual bit-by-bit modifications. Additional files handle data constraints and randomization, used by the simulator in specific UVM phases to generate the NVM data.
This method provides control over NVM content within the UVM framework, independent of simulation tools and programming languages. It achieves comprehensive coverage and drastically reduces the time required for generating NVM content. The innovative approach enhances silicon quality and prevents bugs, making it a versatile solution for any project.
Event Type
Engineering Presentation
TimeMonday, June 232:30pm - 2:45pm PDT
Location2010, Level 2