Presentation
AUTOLNKGEN: Automated Random Linker File Generation Framework for Heterogenous SoC Verification & Validation
DescriptionSystem-on-Chip (SoC) Design Verification (DV) traditionally relies on C-based verification methodologies, where test cases are executed using default linker command file. These linker command file typically map code execution to predefined memory regions. While effective for general testing, this approach often leaves certain memory regions untested, potentially leading to missed corner cases and latent silicon bugs.
This work explores the creation of linker-agnostic test cases and dynamically targeting all executable memory regions applicable to the respective CPU architecture to address this gap. The proposed methodology ensures comprehensive coverage that all test cases are designed to run across diverse memory segments, reducing dependency on fixed linker configurations.
The implementation involves dynamically randomizing linker configurations by extracting executable regions from the memory map into a structured "executable sheet" that specifies size and bounds for each region. Using this information, scripts parse the executable specifications to generate dynamic linkers which are used in test execution of test cases, which are executed in regression, ensuring comprehensive coverage and robustness in the verification process.
The paper emphasizes the significance of this methodology in achieving exhaustive memory coverage, minimizing validation escapes, and improving the overall quality of SoC verification. This approach aims to enhance first-pass success rates by uncovering potential silicon bugs earlier in the verification cycle, ultimately leading to more robust and reliable SoC designs.
This work explores the creation of linker-agnostic test cases and dynamically targeting all executable memory regions applicable to the respective CPU architecture to address this gap. The proposed methodology ensures comprehensive coverage that all test cases are designed to run across diverse memory segments, reducing dependency on fixed linker configurations.
The implementation involves dynamically randomizing linker configurations by extracting executable regions from the memory map into a structured "executable sheet" that specifies size and bounds for each region. Using this information, scripts parse the executable specifications to generate dynamic linkers which are used in test execution of test cases, which are executed in regression, ensuring comprehensive coverage and robustness in the verification process.
The paper emphasizes the significance of this methodology in achieving exhaustive memory coverage, minimizing validation escapes, and improving the overall quality of SoC verification. This approach aims to enhance first-pass success rates by uncovering potential silicon bugs earlier in the verification cycle, ultimately leading to more robust and reliable SoC designs.
Event Type
Engineering Presentation
TimeWednesday, June 2511:00am - 11:15am PDT
Location2008, Level 2
Front-End Design