Presentation
Comprehensive Power Integrity Analysis of a Super Large Scale 2.5DIC with Multi Silicon Bridges Embedded in Organic Interposer
DescriptionUltra-large-scale 2.5DIC designs with multi silicon bridges embedded on organic interposer show excellent application prospects in various fields such as AI, graphics processing, etc., but their development and application also face a series of challenges, and power integrity is one of the key challenges, including:
·High-density interconnect: Integration of multiple SoC/chip modules and memories in a compact space results in high transient current fluctuations, placing extremely high demands on the power delivery network (PDN)
·Noise suppression: Due to high-frequency operation, special attention needs to be paid to the control of power supply noise, especially AC noise and synchronous switching noise
·Dynamic load response: Rapidly changing workloads require PDN to be able to respond quickly and maintain voltage stability
Therefore, we need to consider a number of factors and adopt a series of measures to ensure stable power supply and minimize noise. Silicon bridge not only help realize high-density interconnects but also provide significant advantages in power integrity.
By placing more Deep Trench Capacitor (DTC) on the silicon bridge in close proximity to the point of load, it helps to respond quickly to transient current changes. Silicon bridges can shorten PDN transfer path, they also allow the use of multiple power ground planes, and they extend the power and ground planes directly near each functional module, reducing voltage drop to enhance power supply stability.
In contrast to the traditional verification of the robustness of PDNs at signoff phase only, we use big data analytics EDA tools to perform early analysis of the PDN to establish whether the DTC configuration strategy on the silicon bridge is appropriate, whether the multilayer power and ground planes are effective, and whether the PDN network is at risk, to predict potential problems early in the design and to adjust the design plan in advance. In the mid-design and signoff phases, we can perform power integrity analysis of the entire super huge 2.5DIC system to ensure that the PDN design meets the target impedance requirements.
keywords : 2.5DIC, silicon bridge, power integrity
·High-density interconnect: Integration of multiple SoC/chip modules and memories in a compact space results in high transient current fluctuations, placing extremely high demands on the power delivery network (PDN)
·Noise suppression: Due to high-frequency operation, special attention needs to be paid to the control of power supply noise, especially AC noise and synchronous switching noise
·Dynamic load response: Rapidly changing workloads require PDN to be able to respond quickly and maintain voltage stability
Therefore, we need to consider a number of factors and adopt a series of measures to ensure stable power supply and minimize noise. Silicon bridge not only help realize high-density interconnects but also provide significant advantages in power integrity.
By placing more Deep Trench Capacitor (DTC) on the silicon bridge in close proximity to the point of load, it helps to respond quickly to transient current changes. Silicon bridges can shorten PDN transfer path, they also allow the use of multiple power ground planes, and they extend the power and ground planes directly near each functional module, reducing voltage drop to enhance power supply stability.
In contrast to the traditional verification of the robustness of PDNs at signoff phase only, we use big data analytics EDA tools to perform early analysis of the PDN to establish whether the DTC configuration strategy on the silicon bridge is appropriate, whether the multilayer power and ground planes are effective, and whether the PDN network is at risk, to predict potential problems early in the design and to adjust the design plan in advance. In the mid-design and signoff phases, we can perform power integrity analysis of the entire super huge 2.5DIC system to ensure that the PDN design meets the target impedance requirements.
keywords : 2.5DIC, silicon bridge, power integrity
Event Type
Engineering Presentation
TimeMonday, June 232:15pm - 2:30pm PDT
Location2012, Level 2
AI
Back-End Design
Chiplet