Presentation
Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
DescriptionIn recent years, 3D design disaggregation has become instrumental in improving wafer cost, yields, design flexibility, PPA (power, performance, area). To fully realize the benefits of 3D disaggregation, it is always desired to have a heterogenous 3DIC system, where each die uses a different process technology with its unique advantages that are most suitable for the designs on such die. Historically, the selection of heterogenous 3D disaggregation design boundaries, or "cutlines", are usually determined in a holistic way that may be tedious and unoptimized, and each die was optimized separately as EDA tools generally do not support multiple process technologies during optimization. This would generally result in multiple trials of cutline definition in order to obtain a satisfactory heterogenous 3DIC system. Therefore, a better method to perform concurrent optimize on the entire heterogenous 3DIC design using multiple process technologies with automation. In this work, we demonstrate an automated method to optimize heterogenous 3DIC design PPA using Cadence Cerebrus to perform machine learning based design space exploration. With this methodology, concurrent optimization with multiple process technologies has ben achieved, and hundreds of 3DIC cutline experiments can be performed automatically and simultaneously, greatly reducing the time and effort needed to find an optimized 3DIC cutline configuration. This Cerebrus-based methodology also considers all critical QOR metrics during optimization, such as areal density, macro placements, bump assignment, timing closure, power consumption, IR drop, and thermal dissipation. With this methodology, we are able to find highly optimized heterogenous 3DIC designs with great efficiency and ease.
Event Type
Engineering Presentation
TimeMonday, June 233:45pm - 4:00pm PDT
Location2008, Level 2