Presentation
A Completely Digital, Low-Power, and Low-Area Phase Synchronization Architecture for Meso-Synchronous Clock Domains Supporting Dynamic Frequency Scaling
DescriptionWhen multiple divided clocks are derived from the same oscillator, and distributed across the System on Chip(SOC) using different transistor families, it becomes very hard to balance the multiple clock trees.
All the divided clocks can then be considered as mesochronous, i.e. the ratio between the clocks is known and the phase is unknown but constant.
By treating the 2 clock domains as mesochronous instead of asynchronous, we can easily increase the throughput of the data crossing the mesochronous domains.
This work proposes a phase synchronization architecture for mesochronous clock domains, which has been developed from ground up and is completely digital.
The proposed architecture is very different from the present literature and caters to low power and low area SOCs and is independent of any gate level custom analog designs or technology node.
The proposed phase synchronization scheme can be adjusted for any clock ratio on the fly and is also suitable for sporadic data transfers and not just burst data, thus providing a versatile solution.
The principles of phase detect synchronization is described with respect to ARM's AHB-APB mesochronous bridge, but can be easily extended to sample any data signal crossing mesochronous domains.
All the divided clocks can then be considered as mesochronous, i.e. the ratio between the clocks is known and the phase is unknown but constant.
By treating the 2 clock domains as mesochronous instead of asynchronous, we can easily increase the throughput of the data crossing the mesochronous domains.
This work proposes a phase synchronization architecture for mesochronous clock domains, which has been developed from ground up and is completely digital.
The proposed architecture is very different from the present literature and caters to low power and low area SOCs and is independent of any gate level custom analog designs or technology node.
The proposed phase synchronization scheme can be adjusted for any clock ratio on the fly and is also suitable for sporadic data transfers and not just burst data, thus providing a versatile solution.
The principles of phase detect synchronization is described with respect to ARM's AHB-APB mesochronous bridge, but can be easily extended to sample any data signal crossing mesochronous domains.
Event Type
Engineering Presentation
TimeMonday, June 231:45pm - 2:00pm PDT
Location2010, Level 2