Presentation
Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
DescriptionPower optimization is a critical consideration in modern semiconductor design. Recovering even a fraction of a percent of chip power can significantly impact the chip's cost, feasibility, and overall viability. Buffers to fix hold time violations in scan-test shift paths switch in both functional & scan operation modes. They stay connected to functional paths and consume power for lifetime of the chip. The problem becomes worse in multi-clock domain designs. Functional power dissipation in these parasitic scan-test shift buffers is a waste. Existing EDA tool's ability to identify these parasitic buffers is leveraged to isolate them in functional mode.
An effective technique and automation flow for reducing the dynamic power in contemporary digital designs is presented. Dynamic power saving is achieved without any design or implementation trade-offs. The power recovery is moderate for large sized, medium frequency designs and higher for smaller high frequency blocks. All present and future digital circuits can easily adopt the proposed buffer gating technique without any ramifications. The proposed method is implementation-based techniques which is independent of the chip architecture, design size and technology node. The proposed methodology can be implemented using existing EDA tools and will not impact the design cycle time.
An effective technique and automation flow for reducing the dynamic power in contemporary digital designs is presented. Dynamic power saving is achieved without any design or implementation trade-offs. The power recovery is moderate for large sized, medium frequency designs and higher for smaller high frequency blocks. All present and future digital circuits can easily adopt the proposed buffer gating technique without any ramifications. The proposed method is implementation-based techniques which is independent of the chip architecture, design size and technology node. The proposed methodology can be implemented using existing EDA tools and will not impact the design cycle time.
Event Type
Engineering Presentation
TimeTuesday, June 244:15pm - 4:30pm PDT
Location2012, Level 2
Back-End Design
Chiplet