Presentation
Logic and SRAM Library Generation and Analysis for Digital Design Enablement
DescriptionLiberty (.lib) files are the universally accepted format for representing digital circuits early in chip design flows and form the initial building blocks in implementation and sign off cycles with EDA software. One such application for liberty files is in the design process for Mobile SoCs.
Mobile SoCs present a plethora of unique challenges. First, annual re-design of tape outs are necessary with the newest cutting edge technology nodes. With these advanced nodes, foundry PDK's often evolve rapidly requiring in depth verification to identify any discrepancies (or errors) and maintain compliance with initial design requirements.
Second is the wide range of voltage operations required to push the boundaries of performance and power efficiency. This often requires large sets of PVT libraries to meet design closure, which necessitate full library characterization in some cases, a frequently cost and compute intensive task.
This study details the various approaches explored to address these SoC design challenges. Advanced analysis tools for liberty are utilized for robust and complete verification of new designs, while an AI-driven liberty generations tool is used to accelerate the characterization process without the need for full flow characterization.
Mobile SoCs present a plethora of unique challenges. First, annual re-design of tape outs are necessary with the newest cutting edge technology nodes. With these advanced nodes, foundry PDK's often evolve rapidly requiring in depth verification to identify any discrepancies (or errors) and maintain compliance with initial design requirements.
Second is the wide range of voltage operations required to push the boundaries of performance and power efficiency. This often requires large sets of PVT libraries to meet design closure, which necessitate full library characterization in some cases, a frequently cost and compute intensive task.
This study details the various approaches explored to address these SoC design challenges. Advanced analysis tools for liberty are utilized for robust and complete verification of new designs, while an AI-driven liberty generations tool is used to accelerate the characterization process without the need for full flow characterization.
Event Type
Engineering Presentation
TimeMonday, June 233:45pm - 4:00pm PDT
Location2010, Level 2
IP