Presentation
Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
DescriptionThis paper proposes a Scenario-Based Mixed Signal Layout Generator to address the challenges of high turnaround time (TAT) and limited exploration capabilities in memory analog IP layout design. The proposed method integrates an interactive Abstract UI, an Information Form, and a Scenario Constructor and a placement and routing (P&R) Scenario utilizing Generation APIs. These components enable efficient layout generation by allowing engineers to interactively create desired P&R patterns while handling complex patterns such as optional routing, advanced configurations, and analog constraints.
The work significantly reduces TAT, as demonstrated by experimental results: layout time for Latch-up prevention circuit decreased from 2 hours to 25 seconds, and for Differential Amplifier from 8 hours to 34 seconds. Additionally, pattern modifications for exploration were completed in under 10 minutes, allowing engineers to compare characteristics and select optimal layouts with ease. The proposed methodology enhances productivity, simplifies the design process, and improves the quality of layout design while addressing the growing demand for efficient and scalable analog IP solutions. The approach supports not only manual interaction for tailored pattern generation but also lays the foundation for future automation of layout exploration and characteristic comparison processes.
The work significantly reduces TAT, as demonstrated by experimental results: layout time for Latch-up prevention circuit decreased from 2 hours to 25 seconds, and for Differential Amplifier from 8 hours to 34 seconds. Additionally, pattern modifications for exploration were completed in under 10 minutes, allowing engineers to compare characteristics and select optimal layouts with ease. The proposed methodology enhances productivity, simplifies the design process, and improves the quality of layout design while addressing the growing demand for efficient and scalable analog IP solutions. The approach supports not only manual interaction for tailored pattern generation but also lays the foundation for future automation of layout exploration and characteristic comparison processes.
Event Type
Engineering Presentation
TimeMonday, June 233:30pm - 3:45pm PDT
Location2010, Level 2