Presentation
IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
DescriptionAs the number of AI parameters increases, the need for 2.5D packaging, including multi-HBM, becomes more necessary. There are more than 12,000 bumps in a single HBM, increasing the design complexity of the 2.5D Si-interposer and also affecting PDN Quality. Manual Routing, an existing design methodology, is difficult to optimize the design after Multi-Physics analysis due to large PDN design turn around time (TAT).
In this paper, we propose a new methodology for optimizing the Si-Interposer PDN design based on IR drop results with 3DIC platform. Firstly, we used the PDN Auto Routing feature to design the PDN. Secondly, we established the flow of analyzing System Level IR drop. Lastly, by integrating these two flows into Cadence Integrity 3D-IC Platform, PDN design could be efficiently performed from C4Bump assign to C4Bump fix.
Through PDN Auto-Routing, PDN design time was reduced to less than 3 hours. Compared to HBM3E, PDN Quality improved by 68% and also total TAT of PDN Design from C4Bump assign to fix decreased by 53%. By analyzing IR drop results in the early design stage, we were able to determine the number of layers, effectively reducing manufacturing TAT and cost.
In this paper, we propose a new methodology for optimizing the Si-Interposer PDN design based on IR drop results with 3DIC platform. Firstly, we used the PDN Auto Routing feature to design the PDN. Secondly, we established the flow of analyzing System Level IR drop. Lastly, by integrating these two flows into Cadence Integrity 3D-IC Platform, PDN design could be efficiently performed from C4Bump assign to C4Bump fix.
Through PDN Auto-Routing, PDN design time was reduced to less than 3 hours. Compared to HBM3E, PDN Quality improved by 68% and also total TAT of PDN Design from C4Bump assign to fix decreased by 53%. By analyzing IR drop results in the early design stage, we were able to determine the number of layers, effectively reducing manufacturing TAT and cost.
Event Type
Engineering Presentation
TimeMonday, June 231:30pm - 1:45pm PDT
Location2012, Level 2
AI
Back-End Design
Chiplet