Presentation
UPF Guided Design Editing for Early Low Power Verification Sign Off
DescriptionAt RTL, VC LP makes sure design is correct as per RTL logic and power format UPF. New electrical issues introduced after multi voltage cells (Isolation/Level Shifter) insertion are caught only at post synthesis.
Traditional Low Power performs UPF syntax and sematic checks at RTL stage and structural and integration checks performed at Netlist stage. Catching Low Power issues at later stages can be costly. There is a high demand to catch post-synthesis issues at RTL stage itself and improve accuracy w.r.t netlist stage.
VC LP already has Virtual Instrumentation based Predictive Flow which virtually instruments the Isolation/Level Shifter cells in the design but has certain limitations such as lot of processing in internal crossover database, lacking GUI and TCL support, netlist level checks not supported etc.
Predictive analysis using Design Editing is introduced to catch most issues upfront at RTL rather than after synthesis or P&R stage. Low power elements (Isolation/Level Shifter) get Instrumented in the RTL design to resemble the synthesized netlist design and netlist level checks are performed considering these instrumented cells. All VC LP checks work seamlessly with instrumented design without the need for any special handling and supports GUI, TCL by default.
Customer got excellent results (~99% Accuracy) and Netlist level checks ability with the Design Editing Flow at their RTL design in terms of reducing noise and performing netlist level checks. This produces cleaner design for synthesis and thus less late-stage costly bugs.
Traditional Low Power performs UPF syntax and sematic checks at RTL stage and structural and integration checks performed at Netlist stage. Catching Low Power issues at later stages can be costly. There is a high demand to catch post-synthesis issues at RTL stage itself and improve accuracy w.r.t netlist stage.
VC LP already has Virtual Instrumentation based Predictive Flow which virtually instruments the Isolation/Level Shifter cells in the design but has certain limitations such as lot of processing in internal crossover database, lacking GUI and TCL support, netlist level checks not supported etc.
Predictive analysis using Design Editing is introduced to catch most issues upfront at RTL rather than after synthesis or P&R stage. Low power elements (Isolation/Level Shifter) get Instrumented in the RTL design to resemble the synthesized netlist design and netlist level checks are performed considering these instrumented cells. All VC LP checks work seamlessly with instrumented design without the need for any special handling and supports GUI, TCL by default.
Customer got excellent results (~99% Accuracy) and Netlist level checks ability with the Design Editing Flow at their RTL design in terms of reducing noise and performing netlist level checks. This produces cleaner design for synthesis and thus less late-stage costly bugs.
Event Type
Engineering Presentation
TimeTuesday, June 2410:45am - 11:00am PDT
Location2010, Level 2
Front-End Design
Chiplet