Presentation
Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
DescriptionWith technology evolution and increased complexity of Macros, IPs and Standard cells, the impact of layout parasitics on designs has become dominant.
Layout parasitic analysis is absolutely necessary to guarantee correct design behavior.
Conventional signoff verification tools are slow, difficult to setup and don't sufficiently address the challenges of custom Macro/IP/Std. cell library development flow.
The main pain points in our development flow include visualizing third party Layout Parasitic Extraction (LPE) netlist, ensuring correctness of extraction, locating parasitics that impact design behavior most.
We incorporated novel IC layout analysis techniques in our flow, which resulted into 2x productivity improvement. The total design cycle time has significantly reduced, from weeks to minutes or hours.
This unique approach lets us visualize, locate and optimize parasitics by quickly and easily running multiple iterations during analysis and debugging. It was a game changer as it helped us compare different LPE netlists, including those from different foundries, enabling us to decide on the right foundry for our products.
This innovative approach to parasitic analysis effectively addresses our major reliability concerns by identifying probable latent defects leading to improvements in DFT (Design for Testability). Thus, LPE netlist is no longer a black-box.
Layout parasitic analysis is absolutely necessary to guarantee correct design behavior.
Conventional signoff verification tools are slow, difficult to setup and don't sufficiently address the challenges of custom Macro/IP/Std. cell library development flow.
The main pain points in our development flow include visualizing third party Layout Parasitic Extraction (LPE) netlist, ensuring correctness of extraction, locating parasitics that impact design behavior most.
We incorporated novel IC layout analysis techniques in our flow, which resulted into 2x productivity improvement. The total design cycle time has significantly reduced, from weeks to minutes or hours.
This unique approach lets us visualize, locate and optimize parasitics by quickly and easily running multiple iterations during analysis and debugging. It was a game changer as it helped us compare different LPE netlists, including those from different foundries, enabling us to decide on the right foundry for our products.
This innovative approach to parasitic analysis effectively addresses our major reliability concerns by identifying probable latent defects leading to improvements in DFT (Design for Testability). Thus, LPE netlist is no longer a black-box.
Event Type
Engineering Presentation
TimeMonday, June 234:00pm - 4:15pm PDT
Location2010, Level 2
IP
Similar Presentations