Presentation
Enhancing Verification Efficiency with Garbage-Model Methodology
DescriptionThe increasing complexity of modern VLSI designs, with high gate counts and intricate internal logic, presents significant challenges in verification. Traditional verification flows rely on lengthy regression simulations and manually defined stress scenarios, which are resource-intensive and often fall short in uncovering rare edge-case bugs. The Garbage Model (GM) methodology introduces an innovative approach to accelerate verification and enhance bug detection by injecting synthetic stress at key internal flow control signals.
This semi-random manipulation creates a wide range of corner-case scenarios that are difficult to generate using conventional methods. By targeting critical control points in the design, GM enables faster identification of bugs, achieving high functional coverage with less simulation time. Furthermore, the methodology is versatile, applicable at various levels of design, including block, cluster, and full-chip, and across different phases, such as simulation and emulation.
The GM methodology not only improves simulation efficiency but also reduces verification cycles, ensuring higher confidence in design quality while accelerating project timelines.
This presentation highlights the challenges of traditional verification flows, the innovative features of the GM methodology, and its tangible benefits in terms of productivity, scalability, and design robustness. GM represents a transformative step in verification, empowering teams to meet aggressive time-to-market goals with greater reliability.
This semi-random manipulation creates a wide range of corner-case scenarios that are difficult to generate using conventional methods. By targeting critical control points in the design, GM enables faster identification of bugs, achieving high functional coverage with less simulation time. Furthermore, the methodology is versatile, applicable at various levels of design, including block, cluster, and full-chip, and across different phases, such as simulation and emulation.
The GM methodology not only improves simulation efficiency but also reduces verification cycles, ensuring higher confidence in design quality while accelerating project timelines.
This presentation highlights the challenges of traditional verification flows, the innovative features of the GM methodology, and its tangible benefits in terms of productivity, scalability, and design robustness. GM represents a transformative step in verification, empowering teams to meet aggressive time-to-market goals with greater reliability.
Event Type
Engineering Presentation
TimeWednesday, June 2511:45am - 12:00pm PDT
Location2008, Level 2
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