Presentation
Recalibration of MOSFET Compact Models based on Complex Product-Related Layouts using Bayesian Optimization
DescriptionFoundry Process Design Kit (PDK) defines a set of semiconductor components for integrated circuits design. The high-performance circuits design drives the need for MOSFET PDK compact model recalibration, which can tune multiple model parameters to hit multiple targets beyond the most typical I-V and C-V measurement. However, there is often a discrepancy between chip level hardware performance and the predictions using SPICE simulation from MOSFET compact models. With the scaling of advanced semiconductor technology, the complexity of device structures, physics, and models increases dramatically. Matching circuit level hardware measurements demands accuracy from SPICE simulations.
In this work, we propose a new approach that drives recalibration by matching product circuit targets to minimize the gap between chip level product performance and SPICE model prediction. In addition, our approach integrates accurate PEX netlists into the SPICE simulation used for model recalibration. PEX netlist-based model simulation becomes extremely time consuming for large circuits. To improve the overall efficiency and accuracy, we utilize a parallel Bayesian optimization algorithm and associated software infrastructure to solve this multi-circuit optimization. Our experiments show a massive turn-around-time reduction from weeks to a few days for better model quality as measured by predictions of circuit level metrics.
In this work, we propose a new approach that drives recalibration by matching product circuit targets to minimize the gap between chip level product performance and SPICE model prediction. In addition, our approach integrates accurate PEX netlists into the SPICE simulation used for model recalibration. PEX netlist-based model simulation becomes extremely time consuming for large circuits. To improve the overall efficiency and accuracy, we utilize a parallel Bayesian optimization algorithm and associated software infrastructure to solve this multi-circuit optimization. Our experiments show a massive turn-around-time reduction from weeks to a few days for better model quality as measured by predictions of circuit level metrics.
Event Type
Engineering Presentation
TimeTuesday, June 2410:45am - 11:00am PDT
Location2012, Level 2