Presentation
Accelerating SRAM Design Cycles With Additive AI Technology
DescriptionAs mobile SOC designs increasingly incorporate SRAM, achieving high yield qualification becomes crucial for ensuring performance and reliability. However, the iterative nature of SRAM design cycles, driven by failure corrections, design updates, and technology revisions, often results in substantial computational overhead. This paper introduces an AI-based methodology that accelerates SRAM design verification by leveraging Additive Learning technology. By reusing AI models and results from previous simulations, the methodology significantly reduces the number of simulations required for iterative design changes, achieving simulation speedups of 20X to 67X while maintaining accuracy. The proposed methodology addresses critical challenges in SRAM yield qualification, providing a more efficient, automated, and accurate approach to the verification process, ensuring faster time-to-market without compromising accuracy and quality.
Event Type
Engineering Presentation
TimeMonday, June 2310:30am - 10:45am PDT
Location2010, Level 2
AI
IP