Presentation
An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
DescriptionMulti-die SoCs integrate chiplets with distinct roles, requiring seamless coordination as a single system, which significantly increases verification complexity. The ARM SMMU is critical for memory management in SoCs, demanding architecture-specific configurations for TBU, TCU, and DTI interconnects. These requirements complicate the detection of performance-related issues and inter-die interactions in multi-die systems. Traditional verification methods, such as partial page table checks or waveform-based ACE/AXI attribute analysis, often fail to ensure comprehensive coverage, overlooking critical issues like data integrity and TLB hit/miss accuracy. To address these challenges, we propose an automated and scalable Monitor-and-Checker solution for ARM SMMU verification. The Monitor tracks real-time operations, including page table walks and TLB activity, while the Checker validates ACE/AXI transformations, detects exceptions, and ensures DTI data integrity. Applied to the development of a multi-die SoC with four chiplets, the solution identified 16 critical bugs, including a performance issue previously detectable only in real-use scenarios. Despite the increased complexity of multi-die verification, the solution reduced debugging efforts and ensured successful project completion within the planned schedule.
Event Type
Engineering Presentation
TimeTuesday, June 244:30pm - 4:45pm PDT
Location2010, Level 2