Presentation
Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
DescriptionWith the increasing size and complexity of chip designs, the power budget has become increasingly important during the chip signoff stage. It can significantly impact architecture, layout, packaging, and production. Traditional evaluation methods rely on the netlist and are performed in the later stages of development, including synthesis, placement, routing, and post-simulation. These evaluations typically take 1–3 months or longer, leaving insufficient time to optimize power based on gate-level netlist results. This delay eliminates the opportunity for architectural or algorithmic adjustments.
RTL power estimation offers a fast, simple, and efficient approach to predict power consumption during the RTL design stage. However, there are substantial differences between the RTL code and the final gate-level netlist. Achieving a reasonably good correlation between RTL and netlist power is critical. Various complex backend implementations, such as high-fanout buffer trees and repeaters, significantly affect RTL power estimation. While good correlation has been achieved for registers, memory, and clock power, large discrepancies remain for combinational and buffer logic power in advanced nodes.
In this paper, we present an advanced technology to model complex buffers at RTL stage. Using this approach, the power difference for combinational logic improved from 58.51% to 39.19%, and for buffer logic, from -86.70% to -28.57%. In another design, the power difference for combinational logic improved from 62.28% to 1.20%, and for buffer logic, from -89.81% to -67.78%.
RTL power estimation offers a fast, simple, and efficient approach to predict power consumption during the RTL design stage. However, there are substantial differences between the RTL code and the final gate-level netlist. Achieving a reasonably good correlation between RTL and netlist power is critical. Various complex backend implementations, such as high-fanout buffer trees and repeaters, significantly affect RTL power estimation. While good correlation has been achieved for registers, memory, and clock power, large discrepancies remain for combinational and buffer logic power in advanced nodes.
In this paper, we present an advanced technology to model complex buffers at RTL stage. Using this approach, the power difference for combinational logic improved from 58.51% to 39.19%, and for buffer logic, from -86.70% to -28.57%. In another design, the power difference for combinational logic improved from 62.28% to 1.20%, and for buffer logic, from -89.81% to -67.78%.
Event Type
Engineering Presentation
TimeTuesday, June 2411:00am - 11:15am PDT
Location2010, Level 2
Front-End Design
Chiplet