Presentation
Deterministic On Chip Variation Modeling of Clock Mesh
DescriptionClock mesh are preferable clock distribution methods for high frequency clocks because of lower clock latency/skew and on chip variation tolerance. Static timing analysis can't accurately predict the on-chip variation effect in a clock mesh because of the multi-driven nets. In this submission, Silicon proven custom statistical approach (SPICE Montecarlo simulation based) used to accurately calculate the total on-chip variation effect due to process, voltage, Interconnect and temperature variations across clock mesh. Total uncertainty calculated through above approach is significantly lesser when compared to typical on chip variation penalty with regular clock tree synthesis approach. The reduced clock uncertainty greatly simplifies the timing convergence
Event Type
Engineering Presentation
TimeTuesday, June 242:30pm - 2:45pm PDT
Location2012, Level 2