Presentation
Robust Hard Macro Timing Validation: Early Detection of Issues and Automated Feedback for Integration
DescriptionImplementing designs with complex hard macros, like PHY subsystems, creates challenges for timing closure. Liberty models detail the timing intent, requiring correct arcs for all interface data and clock ports. At the integration level, understanding clock and data paths in these hard macros can be overwhelming. Constraints linting and timing analysis tools often miss issues like missing arcs, risking late detection of top-level timing problems or silicon failure if left unaddressed. For instance, a missing arc on a clock port for a maximum frequency clock can lead to under-constrained designs, while a missing data port arc may leave synchronous paths untimed.
This paper proposes a utility for validating hard macro Liberty models against design goals and a dashboard to aid integrators in establishing top-level constraints. The process involves designers generating a preliminary design intent in XLS format from the STA session, followed by manual review to create a golden reference. Subsequent Liberty revisions are compared to this reference, highlighting discrepancies. Additionally, the methodology generates a clock tree trace from the root to output clock ports, pinpointing missing arcs. This approach leverages Synopsys PrimeTime along with Python and Perl scripts and is applicable to any hard macro design.
This paper proposes a utility for validating hard macro Liberty models against design goals and a dashboard to aid integrators in establishing top-level constraints. The process involves designers generating a preliminary design intent in XLS format from the STA session, followed by manual review to create a golden reference. Subsequent Liberty revisions are compared to this reference, highlighting discrepancies. Additionally, the methodology generates a clock tree trace from the root to output clock ports, pinpointing missing arcs. This approach leverages Synopsys PrimeTime along with Python and Perl scripts and is applicable to any hard macro design.
Event Type
Engineering Presentation
TimeMonday, June 234:30pm - 4:45pm PDT
Location2010, Level 2
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