Presentation
A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
DescriptionEvaluating the tolerance of cryptographic modules in application-specific ICs (ASICs) against side-channel (SC) attacks is typically conducted after silicon manufacturing. However, this post-silicon approach faces two major challenges: the high cost and time required for ASIC production, and the inability to pinpoint the sources of unexpected leakage. Simulation-based SC leakage assessments address these issues by enabling evaluations before manufacturing, allowing for immediate design adjustments if required SC leakage tolerance is not met.
This paper presents a hybrid simulation method that integrates logic-based and transistor-level simulations to overcome the limitations of traditional approaches. The proposed method offers high accuracy in assessing SC leakage at the cryptographic core level while also estimating the signal-to-noise ratio (SNR) across the entire chip. Furthermore, it achieves significantly improved efficiency, generating 1,000 waveforms in 300 hours, which is 282 times higher efficiency compared to conventional chip-level transistor simulations. This hybrid approach enables rapid and precise SC leakage evaluation, facilitating the development of secure cryptographic ASICs with reduced design iteration times and costs.
This paper presents a hybrid simulation method that integrates logic-based and transistor-level simulations to overcome the limitations of traditional approaches. The proposed method offers high accuracy in assessing SC leakage at the cryptographic core level while also estimating the signal-to-noise ratio (SNR) across the entire chip. Furthermore, it achieves significantly improved efficiency, generating 1,000 waveforms in 300 hours, which is 282 times higher efficiency compared to conventional chip-level transistor simulations. This hybrid approach enables rapid and precise SC leakage evaluation, facilitating the development of secure cryptographic ASICs with reduced design iteration times and costs.
Event Type
Engineering Presentation
TimeTuesday, June 243:30pm - 3:48pm PDT
Location2012, Level 2
Back-End Design
Chiplet