Presentation
Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
DescriptionWith the increasing reliance on Artificial Intelligence (AI) and the growth of the automotive industry, the need for Power Delivery Network (PDN) analysis for subsystems that include GPUs, CPUs, DSPs and Modem becomes more pertinent than ever. The traditional PDN simulations are costly and require a lot of resources, this proves to be quite difficult for modern systems that have numerous multiple power domains and billions of devices. This paper introduces Reduced Order Model (ROM) for subsystems which provides same physical and electrical impact as that of detailed model while significantly reducing the node, resistor, and current sink counts. Flat level analysis becomes cheaper and quicker with the ROM, without compromising accuracy. CPU designs simulation suggest that the ROM-based analysis is far more resource efficient than full flat, and can achieve up to 2.5 times improvements in runtime, memory, and disk space usage. Comparing ROM results of Static, Dynamic Vectorless, Package analysis and Grid Resistance checks with full-flat simulations further confirms the efficacy of ROM. Therefore, the methodology enhances the design team productivity, shortens time-to-market, and reduces compute resource costs. Further developments hope to broaden the scope of ROM applications to Electromigration (EM), Electrostatic Discharge (ESD), and 3DIC/2.5D simulations.
Event Type
Engineering Presentation
TimeMonday, June 232:45pm - 3:00pm PDT
Location2012, Level 2
AI
Back-End Design
Chiplet