Presentation
High Figure of Merit Polyphase Decimation Core IP
DescriptionDecimation filter cores running at high frequencies contribute significantly to subsystem area & dynamic power in multi-rate signal processing. Arithmetic computation logic and sequential registers and are primary contributors. Contemporary low area and power techniques for digital filter optimizations are customized for case-to-case basis. There is a need for a universal architecture that significantly improves on figure of merit of all contemporary polyphase decimation digital filters. We propose a high performance, low area, low power with no trade-offs, which is highly optimized for multi-mode filter chain design and reuse across modes. A highly efficient coefficient compression method using n-th order differentiation is illustrated in a modulo CIC and FIR filter combo implementation. Techniques to reuse of Modulo MAC (MMAC) computations across variable signal rates and coefficients are demonstrated.
Event Type
Engineering Presentation
TimeWednesday, June 2511:30am - 11:45am PDT
Location2010, Level 2
IP