Presentation
Guided Vectorless with Multi vector profiling for Memory PDN convergence
DescriptionOptimizing power grids for modern high-performance chips is crucial for both performance and reliability, particularly with the increasing complexity of advanced technology nodes. While denser grids are ideal for managing voltage drops, they often necessitate additional routing tracks, creating layout space constraints and potential timing issues. Memory convergence is particularly critical, given its sensitivity to timing, DRC, and IR. The physical implementation of modern high-performance designs requires numerous time-consuming iterations involving PDN design, IR/Timing analysis, floorplanning, and placement. Accurate identification of the correct switching scenario is vital to prevent over-designing the power grid specification. Utilizing VCD as a reliable source of scenarios for DvD simulations is common, but these simulations can be lengthy (around1ms-100ms), requiring weeks to complete a single iteration. Analyzing VCD for a short duration around the peak power window can be optimistic for memories since the worst memory scenarios can be missed. In this study, we developed a method to profile multiple long vectors to guide a vectorless engine, allowing us to mimic worst-case memory scenarios. This approach reduces the pessimism found in regular vectorless analysis (which typically activates memories with a full 100% toggle rate), while offering significant runtime improvements compared to full-length VCD-based simulations and ensuring 100% switching coverage
Event Type
Engineering Presentation
TimeMonday, June 231:45pm - 2:00pm PDT
Location2012, Level 2