Presentation
Formal signoff for Cross-Module Design logic: A novel approach to manage formal scope in increasingly complex systems
DescriptionIn today's complex IP design, features span across multiple blocks to achieve a certain functionality. It throws up challenges in formal verification to yield conclusive results and coverage sign-off. Having multiple clocks and resets, handling constraints are other concerns in the formal verification. As the feature spans across various blocks, there is a significant increase in the sequential depth of the cone leading to undermined state for most of the properties. To overcome foresaid challenges, this paper talks about various nifty techniques like Black Boxing, Abstractions, advanced AI/ML features like Proof Master and functional coverage merge options. These techniques help in verifying a complex feature in existing design or a new feature added to it.
Methodologies and techniques outlined above were successfully applied to qualify Compliance feature of USB 3.2 Controller. This feature is successfully verified with minimum number of undetermined properties. The functional coverage of formal is merged with simulation and the formal vPlan is back annotated with the master vPlan, to get the comprehensive verification tracking. With this formal approach we were able to expedite the verification process by x2 factor.
Methodologies and techniques outlined above were successfully applied to qualify Compliance feature of USB 3.2 Controller. This feature is successfully verified with minimum number of undetermined properties. The functional coverage of formal is merged with simulation and the formal vPlan is back annotated with the master vPlan, to get the comprehensive verification tracking. With this formal approach we were able to expedite the verification process by x2 factor.
Event Type
Engineering Presentation
TimeTuesday, June 242:15pm - 2:30pm PDT
Location2010, Level 2