Presentation
Novel Clocks and Resets Architecture Model
DescriptionFunctional modeling is vital for early System-on-Chip (SoC) validation, enabling architects to accurately represent design intent. However, modeling the Clock and Reset (CAR) unit—a critical component for synchronizing diverse SoC elements—faces significant challenges. These include managing multiple reset and clock domains, aligning them with initialization requirements, ensuring precise synchronization, and integrating power, safety, and reliability features while adhering to platform-specific constraints.
Despite the availability of detailed architecture specifications, these are not directly translatable into functional models. This results in manual, error-prone processes, misalignment between functional models and architecture intent, and delays in achieving crucial design and validation milestones.
We propose an automated approach to create a self-checking, executable model directly derived from architecture specifications. This approach ensures seamless inheritance of clock and reset requirements, bridging the gap between architecture and functional modeling. By automating this process, we reduce errors, accelerate development, and maintain alignment across architecture and design stages. The solution is scalable and efficient, with applications extending to SystemC model development, power architecture specification, physical design timing analysis, RTL design, and verification domains.
Despite the availability of detailed architecture specifications, these are not directly translatable into functional models. This results in manual, error-prone processes, misalignment between functional models and architecture intent, and delays in achieving crucial design and validation milestones.
We propose an automated approach to create a self-checking, executable model directly derived from architecture specifications. This approach ensures seamless inheritance of clock and reset requirements, bridging the gap between architecture and functional modeling. By automating this process, we reduce errors, accelerate development, and maintain alignment across architecture and design stages. The solution is scalable and efficient, with applications extending to SystemC model development, power architecture specification, physical design timing analysis, RTL design, and verification domains.
Event Type
Engineering Presentation
TimeMonday, June 232:15pm - 2:30pm PDT
Location2010, Level 2