Presentation
Efficient Hardware Fuzzing based on SystemC
DescriptionAs design size and complexity grow, design verification becomes increasingly challenging. For the challenge, hardware fuzzing has emerged as a viable solution to improve coverage by injecting randomized test vectors. However, RTL simulation-based hardware fuzzing is constrained by slow simulation speeds, particularly for large designs. To address this, FPGA-based simulation acceleration for hardware fuzzing has been proposed, but it involves significant overhead in creating testbenches and porting designs to FPGA. This work introduces a simulation-based hardware fuzzing approach based on SystemC to enhance simulation speed. This approach builds on a cycle-accurate SystemC model generated by Verilator. By leveraging transaction-level modeling, the method reduces simulation events at bus interfaces. Moreover, unnecessary events caused by clock toggles and cascading are eliminated without compromising accuracy through an adaptive clock gating mechanism. Experimental results support the effectiveness of the proposed approach, achieving a 7.14× speedup over the baseline to achieve the same level of coverage.
Event Type
Engineering Presentation
TimeWednesday, June 2511:15am - 11:30am PDT
Location2008, Level 2
Front-End Design