Presentation
Refresh your UVM Testbench with a Spritz of Python
DescriptionHardware Description-Language (HDL) environments and simulators have always leveraged non-HDL languages to expand beyond the capabilities of native language features. Since Python is currently the most popular programming language, it's no surprise that there is interest in levering it to extend the capabilities of UVM testbench environments. Python can quickly and easily bring a range of new capabilities to your testbench by leveraging a broad ecosystem of existing libraries for tasks as varied as reading files, such JSON or ELF, and performing numeric manipulation. Capturing test sequences in Python can shorten development iteration time, and make use of existing Python language knowledge. There are several challenges to achieving a full-featured, easy-to-use integration. The two languages use conflicting approaches to concurrent programming, the Python C API is verbose and complex, and the most common integration mechanism involves generating code that is tied to a specific Python version. This paper describes the PyHDL-IF package that implements a bi-directional method-calling interface between Python and SystemVerilog, bridges concurrent-programming differences between the two languages, and removes the need to generate and compile C wrapper code.
Event Type
Engineering Presentation
TimeWednesday, June 2510:30am - 10:45am PDT
Location2008, Level 2
Front-End Design