Close

Presentation

Fear Not! With LLMs, Learning PSS Isn't Scary At All
DescriptionThe adoption of the Portable Stimulus Standard (PSS) language in hardware verification remains constrained by the fear of engineers having to learn a new language. Although PSS holds promise for improving verification efficiency—from block-level components to full SoC integrations—its intricate constructs and relationships frequently hinder widespread deployment. Existing solutions, such as relying on consulting services or leveraging graphical interfaces, still demand deep PSS proficiency and can be both resource-intensive and time-consuming.
This paper introduces a novel approach that harnesses Large Language Models (LLMs) to significantly simplify PSS code creation and accelerate coverage closure. By translating high-level textual descriptions into fully formed, syntactically valid PSS code, our solution reduces the learning curve for verification engineers who are not PSS experts. This method also facilitates code compilation to multiple target environments, both industry-standard UVM and C-based verification environments, further streamlining the transition to PSS. As a result, engineering teams can rapidly adopt PSS without sacrificing thoroughness or correctness, leading to more efficient, consistent, and automated verification workflows.
Our findings demonstrate that LLM-assisted PSS code generation can bridge the gap between domain expertise and language proficiency, thus enabling broader, more effective use of the Portable Stimulus Standard in complex verification scenarios.
Event Type
Engineering Presentation
TimeTuesday, June 244:45pm - 5:00pm PDT
Location2010, Level 2
Topics
AI
Front-End Design
Chiplet