Presentation
Dynamic Optimization of Skew Balancing through an Innovative Correct-by-Construct Path Delay Query Technique
DescriptionSkew- the timing variation among signals, can severely impact the performance and functionality of complex design systems, if not taken care of appropriately. Traditional skew minimization techniques often focus on individual signals and consider one signal as reference leading to sub-optimal results when dealing with a large number of inter-related signals, especially in Mixed Signal designs. Traditional techniques are more post-facto and hence iterative
This paper introduces a novel "correct-by-construct" approach for skew balancing across multiple signals in Mixed-signal SoCs. Mixed-signal SoCs combine analog and digital components, presenting unique challenges in achieving precise timing synchronization.
Our proposed methodology leverages "correct-by-construct" optimization strategies to address the timing paths of multiple signals within a design, thus reducing global skew and minimizing congestion in the digital-analog interface channels. The solution therefore ensures first pass STA timing closure even for complex skew requirements across PVT corners enabling early SDF handoff. This in turn ensures faster time to market, avoids any late design/spec changes and signoff timing distortion. This method is also beneficial for multi-core processor designs such as Processors designs where bus skew balance is critical.
In summary, this comprehensive methodology offers a valuable tool for designers to meet complex timing requirements and enhance the reliability of interface timing in an era of increasing complexity and miniaturization.
This paper introduces a novel "correct-by-construct" approach for skew balancing across multiple signals in Mixed-signal SoCs. Mixed-signal SoCs combine analog and digital components, presenting unique challenges in achieving precise timing synchronization.
Our proposed methodology leverages "correct-by-construct" optimization strategies to address the timing paths of multiple signals within a design, thus reducing global skew and minimizing congestion in the digital-analog interface channels. The solution therefore ensures first pass STA timing closure even for complex skew requirements across PVT corners enabling early SDF handoff. This in turn ensures faster time to market, avoids any late design/spec changes and signoff timing distortion. This method is also beneficial for multi-core processor designs such as Processors designs where bus skew balance is critical.
In summary, this comprehensive methodology offers a valuable tool for designers to meet complex timing requirements and enhance the reliability of interface timing in an era of increasing complexity and miniaturization.
Event Type
Engineering Presentation
TimeTuesday, June 242:45pm - 3:00pm PDT
Location2012, Level 2