Presentation
Accelerated SoC Level Android Home Screen Bring-up, System Software Development and Validation at Pre-Silicon with Advanced Hybrid Emulation Methodology
DescriptionSoC level Android home screen bring-up, system Software development and its validation are usually done at post-silicon stage, which can affect time to market a product, and cost of silicon re-spin. It is also difficult to debug hardware/software design bugs at post-silicon level because of less RTL design visibility. So early software development and its validation is very crucial. Therefore, as a Platform Team, It is essential to have a high speed model of the SoC available months before silicon readiness to initiate Android kernel and system
software development effectively.
In this paper we discuss the available early pre-silicon platform, their limitation, and how the hybrid emulation methodology effectively accelerate home screen and system software development. It highlights techniques and customizations developed to accelerate Android Home Screen boot ,like leveraging high speed virtual memories and boot devices , migrating AFM to QEMU based virtual CPU SS, smart partitioning of SoC design components between hardware(RTL) and Virtual side, advanced clocking techniques, Hardware-Software profiling, and peripheral devices enablement close to silicon.
This paper addresses the challenges encountered in porting silicon level Android boot codes during pre-silicon phase, including silicon like PHY characterization. It also presents the accelerated results achieved by incorporating various techniques and Hardware-Software Optimizations, Highlighting the performance improvements at each stage.
software development effectively.
In this paper we discuss the available early pre-silicon platform, their limitation, and how the hybrid emulation methodology effectively accelerate home screen and system software development. It highlights techniques and customizations developed to accelerate Android Home Screen boot ,like leveraging high speed virtual memories and boot devices , migrating AFM to QEMU based virtual CPU SS, smart partitioning of SoC design components between hardware(RTL) and Virtual side, advanced clocking techniques, Hardware-Software profiling, and peripheral devices enablement close to silicon.
This paper addresses the challenges encountered in porting silicon level Android boot codes during pre-silicon phase, including silicon like PHY characterization. It also presents the accelerated results achieved by incorporating various techniques and Hardware-Software Optimizations, Highlighting the performance improvements at each stage.
Event Type
Engineering Presentation
TimeTuesday, June 243:30pm - 3:45pm PDT
Location2008, Level 2