Presentation
Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
DescriptionPower integrity is a major design challenge at advanced nodes. The designs are becoming increasingly large and complex, along with addition of more computing resources and innovative algorithms to do EM-IR analysis. This results in an unmanageable number of IR drop and EM violations that rely on manual fixing and missed PPA opportunities. One of the major bottlenecks of in-design EM-IR analysis is that it is computationally expensive due to the size and coupled nature of the power network. To overcome these issues, this submission demonstrates novel AI-driven methodology that efficiently identifies the root-cause and categorizes implementation of efficient IR repair methods. The state-of-art Generative-AI technology automatically mitigates IR drop issues early in the design cycle, enabling improved productivity for time-to-market. Staggering >95% IR-drop fix rate was achieved on multiple diverse product line designs (4nm and 5nm nodes) without compromising on Power, Performance and Area. The adapted methodology can be further used on System level designs and perform multi-corner, multi-scenario analysis which makes it compatible for all types of designs.
Acronyms: EM: Electromigration, IR: Current x Resistance(Voltage), AI: Artificial Intelligence, PPA: Power Performance Area
Acronyms: EM: Electromigration, IR: Current x Resistance(Voltage), AI: Artificial Intelligence, PPA: Power Performance Area
Event Type
Engineering Presentation
TimeMonday, June 232:45pm - 3:00pm PDT
Location2012, Level 2
AI
Back-End Design
Chiplet